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SX1211
WIRELESS & SENSING
5.3.3. Rx Processing
If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK
signal is provided.
Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively
on DATA and IRQ_1 pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as
illustrated in Figure 36.
DATA (NRZ)
DCLK
Figure 36: Rx Processing in Continuous Mode
Note that in Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal
even if the DCLK signal is not used by the uC. (bit synchronizer is automatically enabled in Buffered and Packet
mode).
5.3.4. Interrupt Signals Mapping
The tables below give the description of the interrupts available in Continuous mode.
Rx_stby_irq_0
00 (d)
Rx
Sync
IRQ_0
IRQ_1
01
1x
RSSI
-
DCLK
Table 17: Interrupt Mapping in Continuous Rx Mode
Note: In Continuous mode, no interrupt is available in Stby mode
Tx
IRQ_0
IRQ_1
Table 18: Interrupt Mapping in Continuous Tx Mode
-
DCLK
Rev 8 – February 2013
Page 42 of 92
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